Course Overview

This courses combines design techniques and methodology with relevant background concepts of high-speed bus and clock design, including transmission line termination, loading, and jitter, using PCB Design Tools like ORCAD, Allegro PCB Designer Suite.
You will work with IBIS models and complete simulations using tools like, Mentor Graphics HyperLynx / Cadence SIGRITY for Signal Integrity Design, Power Integrity Design and Thermal Analysis & Other topics include managing PCB effects and on-chip termination. This course balances lecture modules with instructor demonstrations and practical hands-on labs.

Who should attend?

Digital designers, board layout designers, or scientists, engineers, and technologists seeking to implement Xilinx solutions. Also end users of Xilinx products who want to understand how to implement high-speed interfaces without incurring the signal integrity problems related to timing, crosstalk, and overshoot or undershoot infractions.

Course Outline :
Part 1 – Signal Integrity 1. Signal Integrity Introduction
• What is High Speed Board Design
• Digital Vs. Analog world
• Various effects on electrical signal
2. Transmission Lines
• Theory Basic transmission line
• Critical Trace Length in the Time Domain
• Critical Trace Length in the Frequency Domain
• Propagation Delay Time on Layers: External & Internal
• PCB Conductors
• Distributed T-Line Representation
• Low Frequency versus High Frequency Return Path
• Lossy Lines vs. Lossless Lines
• Skin Effect, Skin depth calculation
• 10G Traces
3. IBIS Models and SI Tools
• What are IBIS Files?
• IBIS Editor, Steps to Create An IBIS Model
• Reading IBIS Files
• Reviewing SI tools
Lab 1: Invoking HyperLynx
4. Reflections
• Reflection Effects
• Reflection Calculations, Value of Series Resistor
• Trace Termination
• Reflection on Different Topologies: Start, Daisy Chain
Lab 2: Reflection Analysis
5. Crosstalk
• Crosstalk in transmission line
• Capacitive XTalk, Inductive XTalk
• Crosstalk calculation
• XTalk and PCB Layer Stackup
• Technique for Minimizing XTalk
• Lab 3: Crosstalk Analysis
6. Signal Integrity Analysis
• Methods for SI Analysis
• Package Modeling
• Via Modeling
• System Analysis
• Serial Transceiver SI Design Kits
• Memory Interface Analysis – DDR3/2  
7. Power Supply Issues
• Impedance and Inductance of the Power Supply
• Bypass Capacitors – Calculate Bypass Capacitor
• Power Supply on Board Level – Critical Location
• Tool Support – HyperLynx  

8. Signal Integrity Summary Part 2 – Board Design
9. Board Design Introduction
10. FPGA Power Supply
• Power Supply Design Flow
• Power Supply Estimation
• Supply Voltage Generation, General schemes , available
• Power Distribution and Bypassing
• Calculating a Power Supply Filter
• Simulation Tools
Lab 4: Power Analysis
11. FPGA Configuration and PCB
• Configuration Interfaces
• Configuration Memory
• Configuration Applications
• Board Design Issues
12. Signal Interfacing: Interfacing in General
• Combining High-Speed I/O Standards – Equal Standards, Different Standards
• High-Speed Clocks on PCB
• Designing with LVPECL and LVDS
• On-Chip Termination – Single, Series, Split
• Serial I/O (Data and Clock Pins)
• Simultaneous Switching Outputs
13. Signal Interfacing: FPGA-Specific Interfacing
Lab 5: I/O Pin Planning
14. Die Architecture and Packaging
• Die and Package Relationship
• Pin Placement Considerations
15. PCB Details
• PCB Technology
• PCB Traces
• Trace & Via Characteristics
• Layer Stackup and Rules
• FPGA Packages and Routability
16. Thermal Aspects
• Basic principal of Heat Flow
• Thermal Resistance Calculation
• Heat Sink Selection rules
Lab 6: Thermal Design
17. Signal Integrity & Board design checklist
18. Board Design Summary